We are much indebted to XMODEL in developing various analog and interface IPs. With its tight analog-digital interactions and well-defined set of primitives, it has proven particularly useful in verifying complex mixed mode circuits such as equalizer adaptation loops, timing/offset calibration loops, and building models. In addition, compared to conventional multi-bit Verilog models, XMODEL showed about 5x speed-up without compromising accuracy and also worked seamlessly with SystemVerilog-based flows such as Universal Verification Methodology (UVM).

We at Chinese Academy of Sciences use XMODEL for simulating clock-and-data recovery (CDR) loops. XMODEL comes with lots of useful primitives and examples, which make it very easy and convenient to build a complex model like CDR. In addition, the simulation speed is very fast. I enjoy using XMODEL for mixed-signal simulations.

My research group at Sung Kyun Kwan University (SKKU) has used XMODEL to develop/verify several mixed-signal ICs such as referenceless clock and data recovery (CDR) circuits and adaptive equalizers. XMODEL provides various and user-friendly primitive cells, ranging from combination logic gates to blocks with special functions such as an ADC, a VCO, a filter, a channel, etc. The primitives also have design parameters such as a delay, voltage noise, and jitter. Thus, we can emulate the behavior of analog parts simply and accurately, allowing precise verification of whole mixed-signal systems. XMODEL's fast speed is also one of the big merits.

During my PhD study at Sung Kyun Kwan University (SKKU), I have used XMODEL to design and verify PAM4 transceiver architectures. Composing analog models with GLISTER was so easy as I didn't have to learn the SystemVerilog language in full. The main advantage of XMODEL for me was that I could do the modeling of the analog parts and design/verification of the digital parts at the same time and I was able to complete a swift verification of a complex ADC-based receiver including a time-interleaved ADC and DSP. I think the XMODEL's fast speed may even allow the verification of the TX/RX equalizer adaptation at the protocol level, which has not been possible with any other simulators I know due to slow speeds.

When we designed a delay-locked loop (DLL) supporting a large number of operating modes and a relatively high speed for our IC technology node, verifying its correct functionality was a big challenge, since AMS co-simulation took about 16 hours to run a single locking case. Fortunately, XMODEL saved our day as the same simulation using MODELZEN auto-extracted SystemVerilog models took only 5 minutes! We were able to run extensive simulations on the DLL all in SystemVerilog and fix a critical bug causing a start-up failure before the deadline. Thank you, XMODEL!