Empower SystemVerilog with Event-Driven Analog Models

    XMODEL™ is an extension to your existing SystemVerilog simulator such as VCS, NC-Verilog, and Questa/ModelSim, enabling fast and accurate simulation of analog/mixed-signal systems with functional models and/or circuit-level models.

    Since XMODEL™ can perform analog simulation entirely in SystemVerilog without involving SPICE, it is ideally suited for verifying large, complex mixed-signal systems where the mixture of digital and analog poses challenges to the existing tools such as SPICE, Verilog-AMS, and Real-Number Verilog.


Event-Driven Simulation of Analog Models in SystemVerilog

  • XMODEL™ uses revolutionary, patent-pending algorithms to express analog waveforms using functional forms and efficiently compute them in an event-driven fashion.
  • Unlike other analog simulators, XMODEL™ has no conflicting trade-off between the simulation speed and accuracy.
  • For the same level of accuracy, XMODEL™ typically achieves 10~100x speed-up compared to Verilog-AMS or Real-Number Verilog.
  • The simulation is entirely in SystemVerilog and is fully compliant with all SystemVerilog based verification flows, such as UVM.


Quick and Easy Model Building with XMODEL™ Primitives

  • XMODEL™ provides a rich set of primitives that let you build analog models and testbenches with.
  • Just connect them up as building blocks; unlike Real-Number Verilog, virtually no programming is required.
  • XMODEL™ primitives are extensive and parameterized; use them as basic operators to build your own component library!


Circuit-Level Modeling in SystemVerilog

  • Unlike Real-Number Verilog, XMODEL™ allows you to use circuit elements in SystemVerilog such as resistors, capacitors, transistors, and even transmission lines.
  • With circuit-level modeling, you can easily model various analog effects such as loading effects, nonlinearity, switching, and multiple drivers.
  • Yet, the simulation still runs entirely in SystemVerilog without invoking SPICE.


Efficient Time-Domain Noise Simulation

  • XMODEL™ has a unique capability of computing the signal’s statistical property during time-domain simulation, with significant speed-ups over the traditional Monte-Carlo simulations.
  • For instance, it takes only about 10 seconds to estimate the bit-error rate (BER) of a high-speed wireline transceiver down to 10 -12.


XMODEL-SPICE Co-simulation

  • When supported by your SystemVerilog simulator, XMODEL™ modules can interface with SPICE netlists as well as Verilog-AMS or Real-Number Verilog modules.
  • With this co-simulation feature, you can verify your model’s equivalence with the circuit by comparing their respective responses to the same testbench and stimuli written in XMODEL™.


Batch simulation processing with XMULAN

  • XMULAN is an extensive Python library included in the XMODEL™ package that allows you to streamline XMODEL™ simulations and post-process their results.
  • With XMULAN, you can write Python scripts that perform simulations while sweeping parameters, collect results, and post-process them for display or recording.