DVCon U.S. 2023
Feb 27 – Mar 2, Booth #125
DVCon U.S. 2023
Feb 27 – Mar 2
Booth #125
Tutorial
March 2, 2023 13:30-17:00 PM
Harnessing the Power of UVM for AMS Verification with XMODEL
Paper
February 28, 2023 11:00 AM
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers
This tutorial offers hands-on learning for writing UVM testbenches for analog/mixed-signal circuits. It will show that the framework of UVM can be extended to verifying analog circuits simply by using a well-defined fixture module encapsulating the device-under-verification (DUV) model and its AMS instrumentations described with XMODEL primitives.
This paper presents a UVM testbench that can measure the jitter tolerance characteristics of a high-speed wireline receiver model described in SystemVerilog/XMODEL. The measurement of jitter tolerance requires an iterative search and the testbench extends the reactive stimulus technique of UVM to find the maximum sinusoidal jitter that can be tolerated by the receiver system.
Tutorial
March 2, 2023
13:30-17:00 PM
Harnessing the Power of UVM for AMS Verification with XMODEL
This tutorial offers hands-on learning for writing UVM testbenches for analog/mixed-signal circuits. It will show that the framework of UVM can be extended to verifying analog circuits simply by using a well-defined fixture module encapsulating the device-under-verification (DUV) model and its AMS instrumentations described with XMODEL primitives.
Paper
February 28, 2023
11:00 AM
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers
This paper presents a UVM testbench that can measure the jitter tolerance characteristics of a high-speed wireline receiver model described in SystemVerilog/XMODEL. The measurement of jitter tolerance requires an iterative search and the testbench extends the reactive stimulus technique of UVM to find the maximum sinusoidal jitter that can be tolerated by the receiver system.
XMODEL
The fastest way to run analog simulation in SystemVerilog
GLISTER
Build top-down analog models in schematic forms
MODELZEN
Auto-extract bottom-up analog models from your circuits