June 8th, 2021

Webinar on Writing OOP-Style SystemVerilog Testbenches for Analog IPs

Learn how to write an OOP-style SystemVerilog testbench for analog/mixed-signal circuits, performing random and directed tests with analog assertion checks to reach 100% functional coverage.

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February 19th, 2021

Meet XMODEL at DVCON U.S. 2021

December 12th, 2020

Next Year, We’ll Fly Again!

February 27th, 2020

XMODEL Meets Silicon Photonics

December 17th, 2019

Wishing You A Very Merry XMODEL

December 12th, 2018

Wishing You A Great Year Ahead

March 30th, 2018

Meet XMODEL at DAC 2018

December 15th, 2017

Season’s Greetings

April 20th, 2017

XMODEL is coming to DAC 2017

December 20th, 2016

Happy Holidays!