2022/04/18

Jaeha Kim Talks on Efficient Analog/Mixed-Signal Simulation in SystemVerilog with Auto-Generated Models at CICC 2022

The talk is scheduled at 9:00 am PDT on Sunday, April 24, 2022, and addresses ways to auto-extract models from analog circuits and run efficient simulations with them in an event-driven logic simulator like SystemVerilog.

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2021/12/20

Happy Holidays!