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XMODEL offers the best way to verify analog/mixed-signal circuits in SystemVerilog without compromising speed or accuracy. Create SystemVerilog models of your analog circuits in a top-down fashion using GLISTER or in a bottom-up fashion using MODELZEN, and simulate them efficiently and thoroughly along with digital models using a UVM testbench!

Paper: Catching the Elusive Voltage Spike with Analog/Mixed-Signal SVA/PSL Assertions

February 26, 15:30-16:00 / Session 12 / Fir

SystemVerilog Assertions (SVA) excel at checking digital circuits but fall short for analog circuits due to their sampling-based nature. This paper shows how to combine SVA with XMODEL to enable true continuous-time assertion checks, catching even the briefest glitches without compromising simulation speed.