xmodel: Empower SystemVerilog
with Event-Driven Analog Models

xmodel: Empower SystemVerilog with Event-Driven Analog Models

Analog/Mixed-Signal Models


XMODEL Primitives Library


SystemVerilog Simulator


XMODEL Simulation Engine

Simulation Results

XMODEL is an extension to your existing SystemVerilog simulator such as VCS, NC-Verilog/Xcelium, and Questa/ModelSim, enabling fast and accurate simulation of analog/mixed-signal systems with functional models and circuit-level models.

Since XMODEL can perform analog simulation entirely in SystemVerilog without involving SPICE, it is ideally suited for verifying large, complex mixed-signal systems where the mixture of digital and analog poses challenges to the existing tools such as SPICE, Verilog-AMS, and Real-Number Verilog.

Demo Video 1
XMODEL vs Real-Number Verilog

Demo Video 2
Learning XMODEL Primitives with Phase-Locked Loop(PLL) Modeling

Feature 1

Event-Driven Simulation with XMODEL Functional Models

XMODEL uses revolutionary, patented algorithms to express analog waveforms in functional expressions and compute them efficiently in an event-driven fashion.

As a result, the functional models composed with XMODEL primitives in SystemVerilog can achieve up to 10~100x speed-up over Verilog-AMS or Real-Number Verilog, which must compute all the values on the waveform for accurate results.

XMODEL vs Other Simulators

Feature 2

Quick and Easy Model Building with XMODEL Primitives

XMODEL provides a rich set of primitives that you can build analog models and testbenches with. Just connect them up as building blocks; unlike Real-Number Verilog, virtually no programming is required. XMODEL primitives are extensive and parameterized; use them as basic operators to build your own component library!

XMODEL Primitives

Feature 3

Circuit-Level Simulation in SystemVerilog with XMODEL

In addition to the functional primitives, XMODEL also provides a set of circuit-level primitives such as resistors, capacitors, transistors, and even transmission lines. With these circuit-level primitives, one can easily compose models with various analog effects such as loading, nonlinearity, switching, and multiple drivers, which is not directly supported by Real-Number Verilog (a.k.a. wreal models). Yet, the simulation still runs entirely in SystemVerilog without invoking SPICE.

Circuit-Level Modeling

Feature 4

Efficient Time-Domain Noise Simulation

XMODEL has a unique capability of computing the signal's statistical property during time-domain simulation, with significant speed-ups over the traditional Monte-Carlo simulations. For instance, it takes only about 10 seconds to estimate the bit-error rate (BER) of a high-speed wireline transceiver down to 10-12.

Eye Diagram

BER Bathtub

Feature 5

XMODEL-SPICE Co-simulation

When supported by your SystemVerilog simulator, XMODEL modules can interface with SPICE netlists as well as Verilog-AMS or Real-Number Verilog modules. With this co-simulation feature, you can verify your model's equivalence with the circuit by comparing their respective responses to the same testbench and stimuli written in XMODEL.

Feature 6

Batch simulation processing with XMULAN

XMULAN is an extensive Python library included in the XMODEL package that allows you to streamline XMODEL simulations and post-process their results. With XMULAN, you can write Python scripts that perform simulations while sweeping parameters, collect results, and post-process them for display or recording.

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