The Best Way to
Verify Analog Circuits
in SystemVerilog

The Best Way to
Verify Analog Circuits
in SystemVerilog

For Verification Engineers

who want to run faster simulation of analog models in SystemVerilog

XMODEL is the fastest way to run analog simulation in SystemVerilog

Its unique event-driven algorithm and rich set of primitives make it easy to compose analog models that run 10~100x faster than Real-Number Verilog models.

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For System Architects

who need to compose analog models but don't like writing codes

GLISTER lets you build top-down analog models in schematic forms

With GLISTER, writing analog models is simply drawing schematics with XMODEL primitive symbols in Cadence Virtuoso. No coding required!

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For Circuit Designers

who need to write SystemVerilog models for their analog circuits

MODELZEN can auto-extract bottom-up analog models from your circuits

With MODELZEN, you can automatically generate correct-by-construction, SPICE-accurate SystemVerilog models from your circuits just with a mouse click.

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Testimonials

Samsung Electronics, Co., Ltd.
Jongshin Shin, VP, Foundry Division

Chinese Academy of Sciences
Qiwen Liao, Ph.D. Candidate

Sung Kyun Kwan University
Prof. Junghoon Chun

Samsung Electronics, Co., Ltd.
Sungha Kim, Senior Design Engineer

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