I want to run faster simulation of analog models in SystemVerilog

XMODEL™ is the fastest way to run analog simulation in SystemVerilog

Its unique event-driven algorithm supports both functional- and circuit-level simulation 10~100x faster than Real-Number Verilog.

Learn More

I need to compose analog models but don’t want to write codes

GLISTER™ is a graphical user interface integrated into Cadence® Virtuoso®

It lets you build analog models in schematic forms and netlist them in SystemVerilog without writing any codes.

Learn More

I want to auto-extract SystemVerilog models from my circuits

MODELZEN™ is an automatic model generator for analog circuits

It lets you build analog models in schematic forms and netlist them in SystemVerilog without writing any codes.

Learn More

Watch Our Introductory Video

Download Our Product Brochure

English   Korean

Enter your e-mail address to receive our newsletters and updates.