Model of the Month
Delay-locked loop with a false-lock detector
Explore this model of a delay-locked loop (DLL) that can recover from false-lock conditions, based on the design published by S. Byun et al. in 2003. Learn more
August 2026
Q&A of the Month
Modeling power-supply induced jitter (PSIJ) effects in clock buffer chains
Learn how to model the PSIJ effects in a clock distribution network with a 'delay_to_clk' primitive and measure its frequency characteristics using a 'probe_ac' primitive. Learn more
Primitive of the Month
probe_ac
With this primitive, you can measure the frequency-domain transfer function of your circuit/model while running time-domain simulation in SystemVerilog. Learn more
Latest Issues
October 2026
XMODEL at DVCon Europe, Optimal Equalizer Design, and More
September 2026
Modeling a Digital PLL, Handling X/Z Values, and More
August 2026
Modeling DLL, Simulating PSIJ, and More
July 2026
Meet Diana, Scientific Analog's AI Booth Specialist at DAC 2026!
June 2026
Verifying NPUs with CIM, Optimizing Transmit Equalizers, and More