This popular tutorial is now updated with channel crosstalk modeling, voltage-mode transmit equalizer, dither suppression in bang-bang CDRs, and new scripts for BER bathtub, JTRAN, and JTOL simulations.
Here is a simple SystemVerilog testbench that can measure the state and transition coverages of your FSM simulation.
Check out this simple way of limiting the output voltage and slew rate using the new 'vlimit' and 'ilimit' primitives.
This primitive models a nonlinear resistor element which can keep the current flowing through the element within the specified limits.
Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More
Measuring Open-Loop Transfer Function of DC-DC Converter, Extracting Charge-Pump Converter Models, and More
XMODEL at DAC 2025, Modeling an Asynchronous SAR-ADC, and More
Modeling NAND Flash Memory, Measuring Comparator's Offset, and More
Silicon Photonics Simulation with XMODEL, Measuring I-V Curves, and More