Upcoming Event
Meet Scientific Analog at DVCon U.S. 2022
Meet our experts on verifying analog circuits in SystemVerilog/UVM!

Meet our experts on verifying analog circuits in SystemVerilog/UVM!
Seeing is believing! Witness how easy it is to auto-extract models from circuits using MODELZEN.
This primitive can produce digital pulses with periodic or arbitrary waveforms.
Learn how to utilize the new feature of 'pulse_gen' primitive to generate digital pulses with irregular waveforms.
Silicon Photonics Simulation with XMODEL, Measuring I-V Curves, and More
Catching Elusive Voltage Spikes with Assertions, Modeling VCO with Extra Digital Inputs, and More
Modeling Delta-Sigma Digital-to-Analog Converters, XMODEL at DVCon US, and More
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More