March 2026

Video on Demand

Introducing EQCHECK: A Model vs. Circuit Equivalence Checker

This video gives a demo of running EQCHECK on a pipelined ADC example, validating SystemVerilog models against circuits. Learn more

Model of the Month

Here is an example of modeling a DFE receiver with a sign-sign LMS adaptation loop adjusting the filter coefficients. Learn more

Primitive of the Month

This primitive computes the logarithm of an xreal-typed input. Learn more

Estimating Eye Openings and FFE/DFE Settings from Channel SBR

Delay, Delay, Delay!

EQCHECK, Adaptive Decision-Feedback Equalizer, and More

XMODEL at DVCon US, Introducing EQCHECK, and More

Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More