Upcoming Event
Meet Scientific Analog at DVCon U.S. 2022
Meet our experts on verifying analog circuits in SystemVerilog/UVM!
Meet our experts on verifying analog circuits in SystemVerilog/UVM!
Seeing is believing! Witness how easy it is to auto-extract models from circuits using MODELZEN.
This primitive can produce digital pulses with periodic or arbitrary waveforms.
Learn how to utilize the new feature of 'pulse_gen' primitive to generate digital pulses with irregular waveforms.
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More
Webinar on Silicon Photonics Modeling & Simulation, Modeling Nonlinear PAM4 Transmitters, and More
XMODEL at DAC 2024, Modeling an Adaptive DFE Receiver, and More
Modeling a Phase Interpolator with INL/DNL, Using PSL Assertions for Analog Checks, and More