February 2022

Meet Scientific Analog at DVCon U.S. 2022

Meet our experts on verifying analog circuits in SystemVerilog/UVM!

Seeing is believing! Witness how easy it is to auto-extract models from circuits using MODELZEN.

This primitive can produce digital pulses with periodic or arbitrary waveforms.

Learn how to utilize the new feature of 'pulse_gen' primitive to generate digital pulses with irregular waveforms.

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More

Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More