Upcoming Event
Meet XMODEL at DVCon U.S. 2026
Scientific Analog is coming to San Jose, CA! Meet our experts and discover the latest advances in verifying analog circuits with SystemVerilog & UVM. Learn more
February 2026
Application Note
Introducing EQCHECK: A Model vs. Circuit Equivalence Checker
EQCHECK streamlines the validation of SystemVerilog models against SPICE-level circuits. See how it works through a pipelined ADC example. Learn more
Tip of the Month
Using 'xrun' instead of 'xmverilog' to run XMODEL simulations
The latest XMODEL release makes it easy to switch between 'xmverilog' and 'xrun', despite their differences in option formats. Learn more
Primitive of the Month
check_delay
This primitive checks whether the delay difference between two digital signals falls within a specified range. Learn more
Latest Issues
March 2026
EQCHECK, Adaptive Decision-Feedback Equalizer, and More
February 2026
XMODEL at DVCon US, Introducing EQCHECK, and More
January 2026
Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More
December 2025
Season's Greetings, Checking a Clocked Comparator's Correct Output, and More
November 2025
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More