Primitive of the Month
probe_dc
This primitive lets you measure the DC transfer function of your circuit model in a single simulation run.
January 2021
Tip of the Month
Simulating the DC transfer characteristics of a circuit model
Learn how to perform DC analysis on your model and plot its DC transfer function using the new 'probe_dc' primitive and 'meas_dc' script.
Model of the Month
Successive approximation register (SAR) ADC
Check out how to model a SAR ADC made of a charge-redistribution DAC and successive approximation FSM.
XMODEL Release Updates
2021.01 Release
This release introduces 'probe_dc' primitive, adds multiprocessing support for UDMs, and generates parameterized symbol views for Verilog modules with variable port widths.
Latest Issues
August 2025
Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More
July 2025
Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More
June 2025
Measuring Open-Loop Transfer Function of DC-DC Converter, Extracting Charge-Pump Converter Models, and More
May 2025
XMODEL at DAC 2025, Modeling an Asynchronous SAR-ADC, and More
April 2025
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