January 2025

Model of the month

Modeling delta-sigma D/A converters

This application note demonstrates models of various delta-sigma D/A converters and testbenches to simulate their transient, DC, and AC characteristics.

Tip of the Month

Generating a clock with the phase noise of a PLL

Now that you've learned how to shape the phase noise of a clock using an arbitrary transfer function, can you generate a clock that has the phase noise characteristics of a phase-locked loop (PLL)?

Primitive of the Month

clk_to_phase

This primitive outputs the phase of the input clock.

Upcoming Event

Meet Scientific Analog at DVCon U.S. 2025

Don't miss this chance to learn the latest techniques for verifying analog circuits in SystemVerilog & UVM. Charles Dancak is presenting how to catch voltage spikes using XMODEL and SVA.