July 2021

DLL with a replica loop

Check out this model for a delay-locked loop (DLL) that operates over a wide frequency range without false locks using a replica loop, published by Y. Moon, et al. in 2000.

Extracting multi-port transmission line models from S-parameter files

With the new 'sparam_to_tline' utility, you can now extract a multi-port transmission line model including all the port-to-port transfer functions such as reflections and crosstalks from an S-parameter file.

dff_xbit

This primitive models a D-flipflop, with optional setup and hold time violation checks.

2021.07 Release

This release adds the support for UDM mappings on individual slices of parallel instances, and internal current probing for variable RLC and switch primitives.

Latest Issues

March 2024

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

February 2024

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

January 2024

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

December 2023

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More

November 2023

Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More