June 2022

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This application note models the duty-cycle corrector presented by James S. Humble, et al., in their 2006 ISSCC paper.

Check out how to dump the time instants of the clock's transition edges into a text file for post-processing.

This primitive measures the time of each input event being triggered.

This release improves the XMODEL's stability of circuit-level simulation and the MODELZEN support for CDL-format netlists.

Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More

A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More

XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More

Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More

Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More