Upcoming Event
Meet XMODEL at DAC 2022
Meet our experts in person and learn why XMODEL is the best way to verify analog circuits in SystemVerilog!
June 2022
Model of the Month
Modeling a duty-cycle corrector (DCC)
This application note models the duty-cycle corrector presented by James S. Humble, et al., in their 2006 ISSCC paper.
Tip of the Month
Recording the time instants of a clock waveform
Check out how to dump the time instants of the clock's transition edges into a text file for post-processing.
Primitive of the Month
meas_time
This primitive measures the time of each input event being triggered.
XMODEL Release Updates
XMODEL 2022.06
This release improves the XMODEL's stability of circuit-level simulation and the MODELZEN support for CDL-format netlists.
Latest Issues
May 2026
Estimating Eye Openings and FFE/DFE Settings from Channel SBR
April 2026
Delay, Delay, Delay!
March 2026
EQCHECK, Adaptive Decision-Feedback Equalizer, and More
February 2026
XMODEL at DVCon US, Introducing EQCHECK, and More
January 2026
Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More