May 2021

Model of the Month

Delay-locked loop with false-lock detector

This model describes a delay-locked loop (DLL) that can recover from false-lock conditions. It is modeled after the DLL published by S. Byun, et al. in 2003.

Q&A of the Month

Can XMODEL simulate both voltages and currents?

Learn more about the XMODEL's capability of simulating both the voltage and current waveforms of circuit-level models.

Primitive of the Month

abs_func

This primitive computes the absolute value of the xreal-type input.

Upcoming Webinar

Writing OOP-style SystemVerilog testbenches for analog IPs

Join this webinar on how to write an OOP-style SystemVerilog testbench for analog/mixed-signal circuits, performing random and directed tests with analog assertion checks.