Learn UCIe by seeing it in action! This webinar demonstrates the modeling and simulation of the electrical and logical layers of the Universal Chip Interconnect Express (UCIe) PHY in SystemVerilog.
This application note illustrates the process of developing Volterra-series models for nonlinear circuits with XMODEL.
Learn how you can constrain the value space of the UDM's mode bits and make its characterization faster.
With this primitive, you can compute a polynomial function of xreal-type signals.
Silicon Photonics Simulation with XMODEL, Measuring I-V Curves, and More
Catching Elusive Voltage Spikes with Assertions, Modeling VCO with Extra Digital Inputs, and More
Modeling Delta-Sigma Digital-to-Analog Converters, XMODEL at DVCon US, and More
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More