Learn UCIe by seeing it in action! This webinar demonstrates the modeling and simulation of the electrical and logical layers of the Universal Chip Interconnect Express (UCIe) PHY in SystemVerilog.
This application note illustrates the process of developing Volterra-series models for nonlinear circuits with XMODEL.
Learn how you can constrain the value space of the UDM's mode bits and make its characterization faster.
With this primitive, you can compute a polynomial function of xreal-type signals.
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More
Webinar on Silicon Photonics Modeling & Simulation, Modeling Nonlinear PAM4 Transmitters, and More
XMODEL at DAC 2024, Modeling an Adaptive DFE Receiver, and More
Modeling a Phase Interpolator with INL/DNL, Using PSL Assertions for Analog Checks, and More