UCIe PHY Modeling and Simulation with XMODEL
Learn UCIe by seeing it in action! This webinar demonstrates the modeling and simulation of the electrical and logical layers of the Universal Chip Interconnect Express (UCIe) PHY in SystemVerilog.
May 2023
Volterra-series modeling of nonlinear circuits
This application note illustrates the process of developing Volterra-series models for nonlinear circuits with XMODEL.
Mode specification expressions for User-Defined Models (UDM)
Learn how you can constrain the value space of the UDM's mode bits and make its characterization faster.
Latest Issues
April 2024
Modeling an Oscillator with Resettable Phase, Multiple Outputs, and Arbitrary Waveforms
March 2024
UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More
February 2024
XMODEL at DVCon US, Modeling D-PHY Transceivers, and More
January 2024
Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More
December 2023
XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More