Upcoming Event
DAC 2025
Meet us in San Francisco and discover what's new with XMODEL, GLISTER, and MODELZEN! Learn more
May 2025
Model of the Month
Modeling an asynchronous SAR ADC
An asynchronous SAR-ADC uses a self-timed clock to start the next comparison step as soon as the current one completes. How would you model this in SystemVerilog? Learn more
Tip of the Month
Passing a large array of values from one module to another
XMODEL provides a set of DPI functions for dynamic array creation and pointer-based access. Learn more
Primitive of the Month
res_sw
This primitive models a resistor whose resistance is dynamically controlled by an input. Learn more
Latest Issues
March 2026
EQCHECK, Adaptive Decision-Feedback Equalizer, and More
February 2026
XMODEL at DVCon US, Introducing EQCHECK, and More
January 2026
Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More
December 2025
Season's Greetings, Checking a Clocked Comparator's Correct Output, and More
November 2025
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More