TIP OF THE MONTH
How to generate and verify parallel streams of pseudo-random bits
Learn how to generate and verify parallel streams of pseudo-random digital bits using the 'prbs_gen' and 'probe_ber' primitives.
November 2019
PRIMITIVE OF THE MONTH
res_sw, cap_sw, ind_sw
These primitives are handy when modeling passive R, L, C elements whose values change with inputs.
MODEL OF THE MONTH
Continous-time Delta-Sigma ADC
This example demonstrates how to model a switched-capacitor-based delta-sigma modulator (DSM) and simulate it along with a digital decimator in SystemVerilog.
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