November 2019

TIP OF THE MONTH

How to generate and verify parallel streams of pseudo-random bits

Learn how to generate and verify parallel streams of pseudo-random digital bits using the 'prbs_gen' and 'probe_ber' primitives.

Learn more ➔

PRIMITIVE OF THE MONTH

res_sw, cap_sw, ind_sw

These primitives are handy when modeling passive R, L, C elements whose values change with inputs.

Learn more ➔

MODEL OF THE MONTH

Continous-time Delta-Sigma ADC

This example demonstrates how to model a switched-capacitor-based delta-sigma modulator (DSM) and simulate it along with a digital decimator in SystemVerilog.

Learn more ➔

Latest Issues

August 2025

Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More

July 2025

Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More

June 2025

Measuring Open-Loop Transfer Function of DC-DC Converter, Extracting Charge-Pump Converter Models, and More

May 2025

XMODEL at DAC 2025, Modeling an Asynchronous SAR-ADC, and More

April 2025

Modeling NAND Flash Memory, Measuring Comparator's Offset, and More