October 2019

TIP OF THE MONTH

Translating HSPICE or Spectre testbenches into XMODEL’s equivalent testbenches

Find out how MODELZEN converts your SPICE testbenches including .MEASURE and .VEC statements to SystemVerilog testbenches.

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PRIMITIVE OF THE MONTH

vinit, iinit

These primitives are equivalent to a .IC statement in SPICE, which sets the initial condition of a node voltage or branch current.

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MODEL OF THE MONTH

Digitally-Controlled Phase-Locked Loop (PLL)

This example showcases how you can seamlessly combine the models for analog components and digital controller in SystemVerilog using XMODEL.

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Latest Issues

March 2024

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

February 2024

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

January 2024

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

December 2023

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More

November 2023

Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More