October 2019

TIP OF THE MONTH

Translating HSPICE or Spectre testbenches into XMODEL’s equivalent testbenches

Find out how MODELZEN converts your SPICE testbenches including .MEASURE and .VEC statements to SystemVerilog testbenches.

PRIMITIVE OF THE MONTH

These primitives are equivalent to a .IC statement in SPICE, which sets the initial condition of a node voltage or branch current.

MODEL OF THE MONTH

This example showcases how you can seamlessly combine the models for analog components and digital controller in SystemVerilog using XMODEL.

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More

Webinar on Silicon Photonics Modeling & Simulation, Modeling Nonlinear PAM4 Transmitters, and More

XMODEL at DAC 2024, Modeling an Adaptive DFE Receiver, and More

Modeling a Phase Interpolator with INL/DNL, Using PSL Assertions for Analog Checks, and More