November 2020

ARTICLE OF THE MONTH

SystemVerilog OOP Testbench for Analog Filter: A Tutorial (Part 1)

Read this article and learn how to build an OOP-style testbench for analog circuits! Its hands-on example offers basic OOP concepts, testbench guidelines, and practical coding insights.

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PRIMITIVE OF THE MONTH

meas_pp

This primitive measures the peak-to-peak value of a signal within a time interval.

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TIP OF THE MONTH

Mapping UDMs in the technology configuration file

Here is how if you want to define UDM mapping within the technology configuration file.

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MODEL OF THE MONTH

Slew-rate controlled driver

Check out how to model a driver circuit with variable rise/fall times.

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Latest Issues

March 2024

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

February 2024

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

January 2024

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

December 2023

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More

November 2023

Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More