November 2020

ARTICLE OF THE MONTH

SystemVerilog OOP Testbench for Analog Filter: A Tutorial (Part 1)

Read this article and learn how to build an OOP-style testbench for analog circuits! Its hands-on example offers basic OOP concepts, testbench guidelines, and practical coding insights.

Learn more ➔

PRIMITIVE OF THE MONTH

meas_pp

This primitive measures the peak-to-peak value of a signal within a time interval.

Learn more ➔

TIP OF THE MONTH

Mapping UDMs in the technology configuration file

Here is how if you want to define UDM mapping within the technology configuration file.

Learn more ➔

MODEL OF THE MONTH

Slew-rate controlled driver

Check out how to model a driver circuit with variable rise/fall times.

Learn more ➔

Latest Issues

July 2026

Meet Diana, Scientific Analog's AI Booth Specialist at DAC 2026!

June 2026

Verifying NPUs with CIM, Optimizing Transmit Equalizers, and More

May 2026

Estimating Eye Openings and FFE/DFE Settings from Channel SBR

April 2026

Delay, Delay, Delay!

March 2026

EQCHECK, Adaptive Decision-Feedback Equalizer, and More