Q&A OF THE MONTH
Why does MODELZEN turn all the ports into input ports?
Here is a little mystery solved if you've ever wondered about the port directions produced by MODELZEN.
Q&A OF THE MONTH
Here is a little mystery solved if you've ever wondered about the port directions produced by MODELZEN.
TIP OF THE MONTH
A Spectre user? Here is a quick tip on how to get started with MODELZEN.
PRIMITIVE OF THE MONTH
This primitive measures the time of each input event being triggered.
FEATURE OF THE MONTH
Watch this video and learn how the power of XMODEL can be extended to simulating wavelength-division multiplexing (WDM) silicon photonic links in SystemVerilog.
Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More
Season's Greetings, Checking a Clocked Comparator's Correct Output, and More
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More
A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More
XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More