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With XMODEL, modeling analog circuits in SystemVerilog is as easy and fun as skiing. GLISTER lets you carve top-down models, while MODELZEN takes you bottom-up. Then, race through simulation alongside digital models in a UVM testbench, and reach efficient, comprehensive verification of mixed-signal systems!

Paper: A UVM Testbench for Exploring Design Margins of Analog/Mixed-Signal Circuits: A PCI-Express Receiver Detection Circuit Example

October 15, 5:15 PM | Forum 6 | Session 7C

This paper presents a UVM testbench that characterizes the design margin of a PCI-Express receiver detection circuit, by combining a reactive stimulus technique with a Bayesian optimization algorithm and finding the worst-case deviation of the circuit’s response across a continuous parameter space.