Scientific Analog | The Best Way to Verify Analog Circuits in SystemVerilog

October 30th, 2026

Meet Scientific Analog at DVCon Europe 2026

Scientific Analog offers the best way to verify analog/mixed-signal circuits in SystemVerilog. Now, we’re making it even smarter with AI.

Automatically extract models with MODELZEN, validate them against transistor-level circuits with EQCHECK, and run full-chip mixed-signal verification with XMODEL and UVM.

Visit Scientific Analog at Booth #16 to see what’s possible today—and what’s coming next.

Tutorial: Automated Equivalence Checking for Analog/Mixed-Signal Models

November 17, 9:00 AM | Forum 6

Learn how to validate SystemVerilog analog/mixed-signal models against transistor-level circuits using testbenches automatically generated by EQCHECK. Through a pipelined ADC example, this tutorial shows how EQCHECK fits into a complete verification flow with MODELZEN and XMODEL.