May 24th, 2022

Webinar on Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

Scientific Analog, Inc. is sponsoring an IEEE TechInsider Webinar titled, “Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification.” The webinar is scheduled at 15:00-16:30 PM Pacific Time on Tuesday, June 21, 2022, and is given by Charles Dančak, an expert instructor and consultant in SystemVerilog.

This webinar focuses on how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog’s XMODEL.

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