[09-10/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
This webinar addresses how to write an OOP-style SystemVerilog testbench for analog/mixed-signal circuits. The key testbench components such as the test sequence, driver, monitor, and scoreboard are presented in a step-by-step manner. Using a digitally-programmable analog filter as an example, this webinar discusses ways of reaching 100% functional coverage over the digital modes as well as analog inputs with random/directed tests and analog assertion checks.
Section 09: Environment Module
Section 10: OOP/XMODEL Guidelines