probe_dc
This primitive lets you measure the DC transfer function of your circuit model in a single simulation run.
January 2021
Simulating the DC transfer characteristics of a circuit model
Learn how to perform DC analysis on your model and plot its DC transfer function using the new 'probe_dc' primitive and 'meas_dc' script.
Successive approximation register (SAR) ADC
Check out how to model a SAR ADC made of a charge-redistribution DAC and successive approximation FSM.
2021.01 Release
This release introduces 'probe_dc' primitive, adds multiprocessing support for UDMs, and generates parameterized symbol views for Verilog modules with variable port widths.
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