July 2022

Webinar on Demand

Writing UVM/SystemVerilog testbenches for analog/mixed-signal verification

Missed this webinar? Watch this video recording and learn how to write UVM testbenches for analog circuits.

Model of the Month

Modeling CMOS image sensor with sub-pixel architecture

This application note models the CMOS image sensor using sub-pixel architecture, recently published by Yorito Sakano, et al., at ISSCC 2020.

Tip of the Month

Fixing the values of certain digital mode inputs of a UDM

Learn simple mode specification expressions that can fix the values of unused digital mode bits of a UDM.

Primitive of the Month

switch

This primitive models an ideal switch with on and off resistances.

Latest Issues

December 2025

Season's Greetings, Checking a Clocked Comparator's Correct Output, and More

November 2025

Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More

October 2025

A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More

September 2025

XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More

August 2025

Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More