Meet XMODEL at DAC 2022
Meet our experts in person and learn why XMODEL is the best way to verify analog circuits in SystemVerilog!
Meet our experts in person and learn why XMODEL is the best way to verify analog circuits in SystemVerilog!
This application note models the duty-cycle corrector presented by James S. Humble, et al., in their 2006 ISSCC paper.
Check out how to dump the time instants of the clock's transition edges into a text file for post-processing.
This release improves the XMODEL's stability of circuit-level simulation and the MODELZEN support for CDL-format netlists.
UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More
XMODEL at DVCon US, Modeling D-PHY Transceivers, and More
Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More
XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More
Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More