June 2022

Meet XMODEL at DAC 2022

Meet our experts in person and learn why XMODEL is the best way to verify analog circuits in SystemVerilog!

Modeling a duty-cycle corrector (DCC)

This application note models the duty-cycle corrector presented by James S. Humble, et al., in their 2006 ISSCC paper.

Recording the time instants of a clock waveform

Check out how to dump the time instants of the clock's transition edges into a text file for post-processing.

meas_time

This primitive measures the time of each input event being triggered.

XMODEL 2022.06

This release improves the XMODEL's stability of circuit-level simulation and the MODELZEN support for CDL-format netlists.

Latest Issues

March 2024

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

February 2024

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

January 2024

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

December 2023

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More

November 2023

Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More