Webinar on Demand
UCIe PHY Modeling and Simulation with XMODEL
Missed this webinar? Watch the video recording and download the UCIe PHY model in SystemVerilog.
July 2023
Model of the Month
Modeling Charge Pump Circuits in NAND Flash Memories
This application note showcases three different ways of modeling a charge-pump voltage generator circuit.
Tip of the Month
Auto-extracting models with all the top-level ports as real types
With the new '--real' option of MODELZEN, it is handy to create SystemVerilog models of which top-level I/O ports are all real types.
Primitive of the Month
pwl_sel
With this primitive, you can model a nonlinear DC transfer function of a circuit which varies with a set of digital input values.
Latest Issues
August 2025
Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More
July 2025
Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More
June 2025
Measuring Open-Loop Transfer Function of DC-DC Converter, Extracting Charge-Pump Converter Models, and More
May 2025
XMODEL at DAC 2025, Modeling an Asynchronous SAR-ADC, and More
April 2025
Modeling NAND Flash Memory, Measuring Comparator's Offset, and More