Webinar on Demand
UCIe PHY Modeling and Simulation with XMODEL
Missed this webinar? Watch the video recording and download the UCIe PHY model in SystemVerilog.
July 2023
Model of the Month
Modeling Charge Pump Circuits in NAND Flash Memories
This application note showcases three different ways of modeling a charge-pump voltage generator circuit.
Tip of the Month
Auto-extracting models with all the top-level ports as real types
With the new '--real' option of MODELZEN, it is handy to create SystemVerilog models of which top-level I/O ports are all real types.
Primitive of the Month
pwl_sel
With this primitive, you can model a nonlinear DC transfer function of a circuit which varies with a set of digital input values.
Latest Issues
March 2025
Silicon Photonics Simulation with XMODEL, Measuring I-V Curves, and More
February 2025
Catching Elusive Voltage Spikes with Assertions, Modeling VCO with Extra Digital Inputs, and More
January 2025
Modeling Delta-Sigma Digital-to-Analog Converters, XMODEL at DVCon US, and More
December 2024
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
November 2024
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More