August 2023

Tutorial on Demand

Low Drop-Out (LDO) Regulator Modeling

Watch this video and learn how to model LDO regulator circuits and simulate them in SystemVerilog.

Tip of the Month

Modeling a finite-aperture clocked comparator with `'compare'` primitive

Did you know the 'compare' primitive has a finite-aperture mode, which can model a clocked comparator with finite sampling bandwidth and regeneration time?

Primitive of the Month

vlimit

This primitive is equivalent to a pair of anti-parallel clamping diodes, which can keep the voltage between two circuit nodes within specified limits.