Low Drop-Out (LDO) Regulator Modeling
Watch this video and learn how to model LDO regulator circuits and simulate them in SystemVerilog.
August 2023
Modeling a finite-aperture clocked comparator with 'compare' primitive
Did you know the 'compare' primitive has a finite-aperture mode, which can model a clocked comparator with finite sampling bandwidth and regeneration time?
vlimit
This primitive is equivalent to a pair of anti-parallel clamping diodes, which can keep the voltage between two circuit nodes within specified limits.
XMODEL 2023.08
This release adds important bug fixes for XMODEL primitives and improves the support for mapping UDMs via technology configuration file.
Latest Issues
April 2024
Modeling an Oscillator with Resettable Phase, Multiple Outputs, and Arbitrary Waveforms
March 2024
UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More
February 2024
XMODEL at DVCon US, Modeling D-PHY Transceivers, and More
January 2024
Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More
December 2023
XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More