Webinar on Demand
UCIe PHY Modeling and Simulation with XMODEL
Missed this webinar? Watch the video recording and download the UCIe PHY model in SystemVerilog.
July 2023
Model of the Month
Modeling Charge Pump Circuits in NAND Flash Memories
This application note showcases three different ways of modeling a charge-pump voltage generator circuit.
Tip of the Month
Auto-extracting models with all the top-level ports as real types
With the new '--real' option of MODELZEN, it is handy to create SystemVerilog models of which top-level I/O ports are all real types.
Primitive of the Month
pwl_sel
With this primitive, you can model a nonlinear DC transfer function of a circuit which varies with a set of digital input values.
Latest Issues
March 2026
EQCHECK, Adaptive Decision-Feedback Equalizer, and More
February 2026
XMODEL at DVCon US, Introducing EQCHECK, and More
January 2026
Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More
December 2025
Season's Greetings, Checking a Clocked Comparator's Correct Output, and More
November 2025
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More