July 2023

UCIe PHY Modeling and Simulation with XMODEL

Missed this webinar? Watch the video recording and download the UCIe PHY model in SystemVerilog.

This application note showcases three different ways of modeling a charge-pump voltage generator circuit.

With the new '--real' option of MODELZEN, it is handy to create SystemVerilog models of which top-level I/O ports are all real types.

With this primitive, you can model a nonlinear DC transfer function of a circuit which varies with a set of digital input values.

Modeling an Oscillator with Resettable Phase, Multiple Outputs, and Arbitrary Waveforms

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More