Technical Paper
A UVM/SystemVerilog Testbench for an LDO Voltage Regulator
Check out this UVM testbench that performs the line/load transient & regulation tests and IDDQ & PSSR measurements on a low-dropout voltage regulator circuit in a single run.
March 2024
Model of the Month
Modeling a digital buffer with adjustable rise and fall delays
Can you model a buffer stage of which rising and falling delays are individually adjusted by digital inputs?
Tip of the Month
Fixing coarse-resolution waveforms displayed with third-party waveform viewers
Got stair-case waveforms when viewing xreal-type signals with PrimeWave or ViVA? Well, it's not XMODEL to blame.
Primitive of the Month
slice
This primitive continuously compares the two xreal-typed inputs and produces an xbit-type output indicating which one is higher.
Latest Issues
July 2025
Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More
June 2025
Measuring Open-Loop Transfer Function of DC-DC Converter, Extracting Charge-Pump Converter Models, and More
May 2025
XMODEL at DAC 2025, Modeling an Asynchronous SAR-ADC, and More
April 2025
Modeling NAND Flash Memory, Measuring Comparator's Offset, and More
March 2025
Silicon Photonics Simulation with XMODEL, Measuring I-V Curves, and More