Upcoming Event
Join Scientific Analog at DVCon U.S. 2024
Scientific Analog is coming to San Jose, CA! Get up to speed with the latest techniques for verifying analog circuits in SystemVerilog & UVM.
Scientific Analog is coming to San Jose, CA! Get up to speed with the latest techniques for verifying analog circuits in SystemVerilog & UVM.
This application note shows how to model the low-power (LP) and high-speed (HS) transceivers of MIPI D-PHY.
When measuring the frequency of a clock input, why does 'meas_freq' primitive produce twice its frequency value?
Meet Diana, Scientific Analog's AI Booth Specialist at DAC 2026!
Verifying NPUs with CIM, Optimizing Transmit Equalizers, and More
Estimating Eye Openings and FFE/DFE Settings from Channel SBR
Delay, Delay, Delay!
EQCHECK, Adaptive Decision-Feedback Equalizer, and More