GLISTER Online Interactive Demo
Want to introduce GLISTER to your friends? This online interactive demo is easy and fun!
November 2021
Modeling High-Speed Wireline Receiver with CTLE/DFE and Bang-bang CDR
Check out this application note showcasing the model of a high-speed wireline receiver with CTLE/DFE equalization and half-rate bang-bang PLL-based CDR.
clk_gen
This primitive is the all time favorite, generating an xbit-type clock with optional sinusoidal jitter and random phase noise.
2021.11 Release
This release adds various improvements related to high-speed I/O modeling, such as the faster eye diagram plotting with XWAVE.
Latest Issues
March 2024
UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More
February 2024
XMODEL at DVCon US, Modeling D-PHY Transceivers, and More
January 2024
Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More
December 2023
XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More
November 2023
Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More