Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits
Missed this webinar? Watch this video recording and gain insights on how to extract models from analog circuits.
October 2021
Converting an xbit/bit signal to an xreal signal with variable levels
The connect primitives with names ending in '_var' support variable conversion levels.
Time to Meet XMODEL at DAC 2021
Don't miss this opportunity to check out the latest updates on XMODEL, GLISTER, and MODELZEN face-to-face!
Latest Issues
March 2024
UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More
February 2024
XMODEL at DVCon US, Modeling D-PHY Transceivers, and More
January 2024
Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More
December 2023
XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More
November 2023
Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More