October 2019

TIP OF THE MONTH

Translating HSPICE or Spectre testbenches into XMODEL’s equivalent testbenches

Find out how MODELZEN converts your SPICE testbenches including .MEASURE and .VEC statements to SystemVerilog testbenches.

PRIMITIVE OF THE MONTH

These primitives are equivalent to a .IC statement in SPICE, which sets the initial condition of a node voltage or branch current.

MODEL OF THE MONTH

This example showcases how you can seamlessly combine the models for analog components and digital controller in SystemVerilog using XMODEL.

Verifying NPUs with CIM, Optimizing Transmit Equalizers, and More

Estimating Eye Openings and FFE/DFE Settings from Channel SBR

Delay, Delay, Delay!

EQCHECK, Adaptive Decision-Feedback Equalizer, and More

XMODEL at DVCon US, Introducing EQCHECK, and More