December 20th, 2021

Happy Holidays!

Latest Issues

May 24th, 2022

Webinar on Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

May 23rd, 2022

Researchers at the Chinese Academy of Sciences Publish Another 50-Gb/s PAM4 Silicon Photonic Transmitter and CDR Designed with XMODEL

April 18th, 2022

Jaeha Kim Talks on Efficient Analog/Mixed-Signal Simulation in SystemVerilog with Auto-Generated Models at CICC 2022

February 17th, 2022

Meet Scientific Analog at DVCon U.S. 2022

January 18th, 2022

Scientific Analog Joins Accellera