January 10th, 2022

Charles Dancak Presents UVM Testbench for AMS Verification at DVCon U.S. 2022

Scientific Analog, Inc. is pleased to announce that Charles Dancak, a renowned consultant and instructor with expertise in SystemVerilog-based verification, will be presenting a UVM testbench for AMS verification at the upcoming 2022 Design and Verification Conference & Exhibition United States (DVCon U.S.). His testbench combines Scientific Analog’s XMODEL with the standard UVM framework, and performs a thorough coverage-based verification with scoreboard and assertion checks on an analog/mixed-signal circuit entirely in SystemVerilog. Mr. Dancak’s talk is scheduled at 9:00 am on Tuesday, March 1, 2022. Due to COVID-19, the conference will be held virtually.

“Charles has set a great example on how to write a UVM-style testbench for AMS circuits that is easy for both digital verification engineers and analog circuit designers. All the analog specifics are encapsulated within the fixture surrounding the DUT, which is easy for circuit designers, and the rest of the testbench is pure UVM components, which is easy for verification engineers", said Jaeha Kim, CEO and Founder of Scientific Analog, Inc.

Scientific Analog, Inc. is a leading developer and provider of a mixed-signal simulator in SystemVerilog (XMODEL), automatic model generator (MODELZEN), and schematic-based modeling environment (GLISTER). DVCon is the premier conference focusing on the languages, tools, methodologies, and standards for design and verification of electronic systems and integrated circuits. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. Charles Dancak teaches SystemVerilog at UC San Diego Extension and is a consultant at Betasoft Consulting, Inc.

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