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SK Hynix, Inc., jointly with Seoul National University and Scientific Analog, will be presenting its case of verifying production DRAM peripheral circuits with automatically-generated SystemVerilog models at the 2018 Design Automation Conference. The DRAM verification flow consists of automatically generating correct-by-construction models using MODELZEN and performing efficient simulation in SystemVerilog using XMODEL.

The case study will be presented in the Designer/IP Track Poster Session held on Wednesday, June 27, 2018 from 5:00pm to 6:00pm on Level 2 Exhibit Floor.

Scientific Analog, Inc. is a leading developer and provider of a mixed-signal simulator in SystemVerilog (XMODEL), automatic model generator (MODELZEN), and schematic-based design environment (GLISTER). SK Hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), Flash memory chips (“NAND Flash”) and CMOS Image Sensors (“CIS”).

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