June 8th, 2021

Webinar on Writing OOP-Style SystemVerilog Testbenches for Analog IPs

Scientific Analog, Inc. is sponsoring an IEEE TechInsider Webinar titled, “Mixed-Signal Verification of Analog IP using SystemVerilog: An Object-Oriented Approach.” The webinar is scheduled at 12:00-13:30PM Pacific Daylight Time (PDT) on Friday, June 25, 2021, and is given by Charles Dančak, an expert instructor and consultant in SystemVerilog.

This webinar focuses on how to write an OOP-style SystemVerilog testbench for analog/mixed-signal circuits. The key testbench components such as the test sequence, driver, monitor, and scoreboard are presented in a step-by-step manner. Using a digitally-programmable analog filter as an example, the webinar discusses ways of reaching 100% functional coverage over the digital modes as well as analog inputs with random/directed tests and analog assertion checks.

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