September 3rd, 2021

Webinar on Auto-Generating SystemVerilog Models from Analog/Mixed-Signal Circuits

Jaeha Kim, the CEO and Founder of Scientific Analog, will be presenting a webinar titled, "Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example." The webinar is scheduled at 18:00-19:00PM Pacific Daylight Time (PDT) on Wednesday, September 15, 2021. The event is sponsored by the IEEE Silicon Valley Solid-State Circuits Society (SSCS).

The webinar addresses how to extract SystemVerilog models automatically from analog/mixed-signal circuits, and perform efficient verification of mixed-signal SoC's using digital flows, such as UVM. It will introduce two modeling approaches, structural and functional, and demonstrate how these approaches work together using a pipelined analog-to-digital converter example.

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