Designers’ Forum

January 23, 16:45-17:10 / Room 110/111

Addressing Modeling and Simulation Challenges in Chiplet Interfaces

High-speed die-to-die interfaces are essential in enabling chiplets, the emerging building blocks for heterogeneous integration. Interestingly, many chiplet interface standards including Universal Chiplet Interconnect Express (UCIe) are evolving in ways so that the analog circuits become standardized blocks, and the digital finite-state machines (FSMs) provide complex functionalities. While such architecture can improve design efficiency and portability, it presents new challenges for verifying the overall system functionalities. This talk will use an example of modeling both the analog circuits and digital FSMs of a UCIe physical layer in SystemVerilog and discuss how one can combine the analog and digital approaches to functional verification.

Exhibit

January 23-25 / 2F Premier Ballroom Lobby