Meet Scientific Analog at DVCon U.S. 2023
Scientific Analog is coming to San Jose, CA! Grab this opportunity to meet our experts on verifying analog circuits in SystemVerilog & UVM.
Scientific Analog is coming to San Jose, CA! Grab this opportunity to meet our experts on verifying analog circuits in SystemVerilog & UVM.
Wondering how far the simulation has run? You can enable a progress display just with a mouse click.
This simple example demonstrates the pulling behavior of an ILO where the phase and frequency of the ILO exhibit beat notes instead of locking at constant values.
This primitive models an injection-locked oscillator with multiple injection inputs and multiple phase outputs.
UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More
XMODEL at DVCon US, Modeling D-PHY Transceivers, and More
Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More
XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More
Modeling a Thermal Sensor Circuit, Measuring the Transmitter Output Resistance, and More