Upcoming Event
Meet Scientific Analog at DVCon U.S. 2023
Scientific Analog is coming to San Jose, CA! Grab this opportunity to meet our experts on verifying analog circuits in SystemVerilog & UVM.
Scientific Analog is coming to San Jose, CA! Grab this opportunity to meet our experts on verifying analog circuits in SystemVerilog & UVM.
Wondering how far the simulation has run? You can enable a progress display just with a mouse click.
This simple example demonstrates the pulling behavior of an ILO where the phase and frequency of the ILO exhibit beat notes instead of locking at constant values.
This primitive models an injection-locked oscillator with multiple injection inputs and multiple phase outputs.
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More
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XMODEL at DAC 2024, Modeling an Adaptive DFE Receiver, and More
Modeling a Phase Interpolator with INL/DNL, Using PSL Assertions for Analog Checks, and More