February 2024

Upcoming Event

Scientific Analog is coming to San Jose, CA! Get up to speed with the latest techniques for verifying analog circuits in SystemVerilog & UVM.

This application note shows how to model the low-power (LP) and high-speed (HS) transceivers of MIPI D-PHY.

When measuring the frequency of a clock input, why does 'meas_freq' primitive produce twice its frequency value?

This primitive outputs the frequency of the input clock.

Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More

A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More

XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More

Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More

Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More