February 2024

Upcoming Event

Scientific Analog is coming to San Jose, CA! Get up to speed with the latest techniques for verifying analog circuits in SystemVerilog & UVM.

This application note shows how to model the low-power (LP) and high-speed (HS) transceivers of MIPI D-PHY.

When measuring the frequency of a clock input, why does 'meas_freq' primitive produce twice its frequency value?

This primitive outputs the frequency of the input clock.

EQCHECK, Adaptive Decision-Feedback Equalizer, and More

XMODEL at DVCon US, Introducing EQCHECK, and More

Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More

Season's Greetings, Checking a Clocked Comparator's Correct Output, and More

Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More