Technical Paper
A UVM/SystemVerilog Testbench for an LDO Voltage Regulator
Check out this UVM testbench that performs the line/load transient & regulation tests and IDDQ & PSSR measurements on a low-dropout voltage regulator circuit in a single run.
March 2024
Model of the Month
Modeling a digital buffer with adjustable rise and fall delays
Can you model a buffer stage of which rising and falling delays are individually adjusted by digital inputs?
Tip of the Month
Fixing coarse-resolution waveforms displayed with third-party waveform viewers
Got stair-case waveforms when viewing xreal-type signals with PrimeWave or ViVA? Well, it's not XMODEL to blame.
Primitive of the Month
slice
This primitive continuously compares the two xreal-typed inputs and produces an xbit-type output indicating which one is higher.
Latest Issues
September 2024
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
August 2024
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More
July 2024
Webinar on Silicon Photonics Modeling & Simulation, Modeling Nonlinear PAM4 Transmitters, and More
June 2024
XMODEL at DAC 2024, Modeling an Adaptive DFE Receiver, and More
May 2024
Modeling a Phase Interpolator with INL/DNL, Using PSL Assertions for Analog Checks, and More